Referring to FIG. 1, a printed circuit board assembly (PCBA), according to the conventional art is shown. As depicted in FIG. 1, the printed circuit board assembly includes a printed circuit board (PCB) 110, integrated circuits (ICs) 120, 125, connectors 130 and the like. The integrated circuits 120, 125 may for example include a central processing unit (CPU), a graphics processing unit (GPU), control circuits, interface circuits (e.g., a north bridge, south bridge or the like), memory and/or the like. The PCB consists of a substrate that has a plurality of traces 140 for interconnecting the ICs 120, 125 and connectors. The traces 140 and the ICs 120, 125 are interconnected to form a given circuit. Typical interconnections (e.g., interface) between one or more ICs and/or a connector include a bus (e.g., system bus, accelerated graphics bus, peripheral component interface, and the like). The bus typically provides for transmission of one or more data signals, address signals and control signals. The timing relationship between the data signals, address signals and the control signals is typically important to proper operation of the circuit.
Referring now to FIG. 2, a timing diagram illustrating exemplary signals on a bus, according to the conventional art, is shown. As depicted in FIG. 2, the relationship between a DQS control signal 210, 215 and data signals for a write and/or read operation are illustrated. For double data rate write operation the transitions of the DQS control signal 210 are aligned midway between the transitions of the data signals 220. Similarly, for a read operation, the transitions of the DQS control signal 215 are aligned with the transitions of the data signals 225. Typically, the DQS signals 210, 215 are derived from a clock signal. A delay lock loop (DLL) cell may be utilized to delay the clock signal a quarter of a cycle to obtain the DQS signal 210, 215. The DLL cell may also provide for a programmable fine adjustment of the delay in accordance with a stored programming value (e.g., qualified setting). The stored programming value is typically a static value stored in memory (e.g., basic input/output system (BIOS)).
Printed circuit board assembly (PCBA) technology continues to evolve at a rapid pace, continually pushing the various electrical interfaces to higher and higher frequencies. Typically, a programming value for generating a set of timing parameters is determined from a number of qualification samples, and is then applied as a qualified setting across all PCBAs. Due to standard application specific integrated circuit (ASIC) and printed circuit board (PCB) manufacturing tolerances and normal process variations, the industry is reaching the limits where a design using a static qualified setting determined in the product qualification phase is no longer sufficient to guarantee proper operation of a given design across variances in a mass production environment.